1. Field of the Invention
This invention relates generally to semiconductor devices and fabrication methods therefor, and more particularly, to a semiconductor device that serves as a non-volatile memory with the use of a transistor having multiple charge storage layers and a fabrication method therefor.
2. Description of the Related Art
Recently, non-volatile memories in which data is rewritable have been widely used. In the technical field of non-volatile memories, efforts are being made to miniaturize a memory cell for high memory capacity and to reduce fluctuation in electrical characteristics of a transistor incorporated in the memory. The non-volatile memories include Metal Oxide Nitride Oxide silicon (MONOS) flash memories and Silicon Oxide Nitride Oxide silicon (SONOS) flash memories, in which the charge is stored in an Oxide Nitride Oxide (ONO) film. In addition, another type of flash memory having two or more charge storage regions in one transistor has been developed for the purpose of high memory capacity.
U.S. Pat. No. 6,011,725 discloses an example of a transistor having two charge storage regions arranged between a gate electrode and a semiconductor substrate. In the transistor, a source and a drain are replaced by each other for symmetrical operation for a structure in which a source region and a drain region are not distinguished. In addition, a bit line also serves as the source region and the drain region and is embedded in a semiconductor substrate to further miniaturize the memory cell.
Referring now to FIG. 1, the aforedescribed conventional semiconductor device will be described. FIG. 1 is a top view of a conventional memory cell. Bit lines 44 are embedded in the semiconductor substrate and are arranged in an upward and downward direction. An ONO film (not shown) is provided over the semiconductor substrate. Word lines 46 are provided on the ONO film to run in a width direction of the bit line 44.
The bit line 44 is formed in a diffusion layer by implanting, for example, arsenic ions, and has a relatively high resistance value. The high resistance value of the bit line 44, however, deteriorates writing and erasing characteristics. Therefore, a contact hole 48 provided for multiple word lines 46 couples the bit line 44 to an interconnection layer (not shown). The interconnection layer is made of a metal and is low in resistance, making it possible to prevent writing and erasing characteristics from deteriorating.
The contact hole 48, which couples the bit line 44 and the interconnection layer, is provided in a bit line contact region 28. The bit line contact region 28 runs in a length direction of the word line 46. A word line region 26 is arranged between the bit line contact regions 28. The word line region 26 does not include the contact hole 48 that couples the bit line 44 and the interconnection layer, in multiple word lines 46 (e.g., two word lines in FIG. 1).
The bit line 44 includes a source region and a drain region of a transistor 50. The word line 46 includes a gate electrode of the transistor 50. The memory serves as a non-volatile memory by storing the charge in the ONO film below the word line 46 (gate electrode) arranged between the bit lines 44 (the source region and the drain region). The ONO film in the transistor 50 includes two charge storage regions.
Conventionally, however, if the contact hole 48 and the bit line 44 are misaligned and the contact hole 48 is out of the bit line 44, junction current will flow between the bit line 44 and the semiconductor substrate. To prevent such junction current, an alignment margin provided between the contact hole 48 and the bit line 44 is required, even though such alignment margin is contrary to the purpose of miniaturization of the memory cell, thereby rendering it difficult to downsize the memory cell.